1. Field of the Invention
The present invention relates to a nonvolatile memory device and an operating method thereof, and more particularly, to a high density nonvolatile memory device which can perform byte erasing and an operating method thereof.
2. Description of the Related Art
Semiconductor memory devices are largely divided into RAMs (Random Access Memories) such as DRAMs (Dynamic RAMs) and SRAMs (Static RAMs), and ROMs (Read Only Memories) including PROMs (Programmable ROMs), EPROMs (Erasable PROMs), and EEPROMs (Electrically Eraseable PROMs). RAMs are referred to as volatile memories in that data is destroyed with passage of time. ROMs retain data once it is entered. Among such ROMs, demand for EEPROMs and flash memory cells is increasing.
Flash memory cells can be of a NOR type or a NAND type. The NAND type flash memory cell, useful for realizing high integration, includes a unit string composed of n cells connected in series. Unit strings are connected in parallel between bit lines and ground lines. The NOR type flash memory cell, providing high-speed operation, has cells connected in parallel between bit lines and ground lines.
A description of the structure and operation of a basic NOR flash memory cell, proposed by Excel Co., in 1985, disclosed in IEDM'85, pp. 6I6.about.619, "A Single Transistor EPROM Cell And Its Implementation In A 512K CMOS EEPROM," will hereinbelow be given in conjunction with FIGS. 1 to 3. FIG. 1 is a partial schematic layout diagram of a memory cell array in a known NOR flash memory device, FIG. 2 is an equivalent circuit diagram of the memory cell array of FIG. 1, and FIG. 3 is a schematic cross-sectional view of a unit cell. Here, reference numeral 10 denotes a semiconductor substrate, reference numeral 11 denotes an active source region, reference numeral 14 denotes a tunnel oxide film, reference numeral 16 denotes a floating gate, reference numeral 18 denotes an interpoly dielectric layer, reference numeral 20 denotes a control gate, reference numerals 24a and 24b denote source and drain regions, respectively, and reference numeral 28 denotes a bit line contact.
Referring to FIGS. 1 to 3, a unit cell having a stacked gate structure of the floating gate 16 and the control gate 20 is formed in an area where the word line W/L perpendicularly intersects the bit line B/L formed of a metal in memory cell arrays, each memory cell array having word lines W/L, source lines CSL, and a plurality of bit lines B/L arranged at specified intervals. Two cells are connected to the bit line B/L by the single bit line contact 28, and the active source region 11 formed of an impurity layer and disposed in parallel with the word line W/L, is connected by the source line CSL arranged in every tens of bits and in parallel with the bit line B/L.
In a unit cell, the tunnel oxide film 14 is interposed between the floating gate 16 and the substrate 10, and the interpoly dielectric layer 18 is interposed between the floating gate 16 and the control gate 20 acting as a word line W/L. The source and drain regions 24a and 24b are formed in self-alignment with the stacked gate. The floating gate 16 extends across an active region and portions of the edges of field regions at both sides of the active region, thus being isolated from that of an adjacent cell. The control gate 20 i, connected to that of an adjacent cell, thus forming a word line W/L.
Adjacent cells are formed in opposite directions, sharing the source/drain regions 24a and 24b. The drain region 24b of a unit cell is connected to that of an adjacent cell in the same row, and has the bit line contact 28 formed therein. Bit line contacts 28 in the same row are electrically connected by the bit line B/L perpendicular to the word line W/L. That is, two cells are connected to the bit line B/L by a single bit line contact 28.
The source region 24a of the unit cell is connected to that of an adjacent cell in the same column through the active source region 11 formed of an impurity diffusion layer parallel to the word line W/L. In addition, to reduce the resistance of the source line, a single source line contact 29 is formed in the active source region 11 parallel to the word line W/L, for a plurality of bit lines B/L. The source line CSL parallel to the bit line B/L is electrically connected to the active source region 11 through the source line contact 29.
Such a general NOR flash memory cell is programmed by CHE (channel hot electron) injection and erased through a source or a bulk substrate by Fowler-Nordheim tunnelling. For a programming operation, the threshold voltage Vth of a cell is increased from an initial level, about 2V, to about 7V by storing electrons on the floating gate 16. That is, by applying 6.about.7V to the selected bit line B/L and 10.about.12V to the selected word line W/L, and 0V to the source and the bulk substrate, parts of the CHEs are introduced into to the floating gate 16 via the tunnel oxide film 18. Thus, the cell is programmed.
For an erasing operation, the threshold voltage Vth of the cell is dropped to the initial level, about 2V, by removing electrons from the floating gate 16. That is, by floating the selected bit line B/L and applying 12.about.15V to the source and 0V to the selected word line W/L, the electrons are removed, by Fowler-Nordheim tunnelling, from the floating gate 16 to the source junction via the tunnel oxide film 18 of about 100 .ANG., due to a potential difference between the floating gate 16 and the source junction. Typically, the source junctions of all cells are electrically connected to one another by the active source region 11, such that all cells of a chip are collectively erased, or the chip is divided into a plurality of blocks in the direction of word line or bit line, to collectively erase the cells in the unit of block.
A reading operation refers to determining the presence or absence of a current path through erased and programmed cells by applying about 1V to the selected bit line B/L and 4.about.5V to the word line W/L.
Here, the common source line CSL serves to discharge a large amount of current generated via the cells during a programming operation, to a ground rode. To discharge a large amount of current in a short time in the flash memory cell using CHE injection, one common source line CSL is formed every tens of bits, e.g., every 16.about.32 bits.
Hereinbelow, a description will be given to a cell structure in a conventional EEPROM device. FIG. 4 is an equivalent circuit diagram of a part of a memory cell array in a conventional EEPROM device, and FIG. 5 is a schematic cross sectional view of a unit cell. Here, reference numeral 50 denotes a semiconductor substrate, reference numeral 52 denotes a tunnel oxide film, reference numeral 53 denotes a gate oxide film, reference numeral 54 denotes a floating gate, reference numeral 56 denotes an interpoly dielectric layer, reference numeral 58 denotes a control gate and reference numerals 62a and 62b denote source/drain regions.
Referring to FIGS. 4 and 5, a unit cell composed of two transistors is formed in an area where word lines W/L perpendicularly intersect bit lines B/L. That is, the unit cell is composed of a select transistor connected to a bit line contact and a memory cell transistor connected to the active source region.
The memory cell transistor is a stacked gate structure where the floating gate 54 is formed on the semiconductor substrate 50 with interposition of the tunnel oxide film 52. The control gate 58 is stacked over the floating gate 54 with interposition of the interpoly dielectric layer 56. The source region 62a of the memory cell transistor is connected to the common source line CSL via the active source region.
The floating gate 54 and the control gate 58 are coupled by a metal line through a butting contact on a field region of the cell array, because the select transistor requires no floating gate for storing data. Hence, the select transistor operates as a MOS transistor having a single-layer gate 60 in electrical terms. In addition, to prevent the tunnelling to the gate 60 of the select transistor, the gate oxide film 53 of the select transistor is formed to be thicker than the tunnel oxide film 52 of the memory cell transistor. The drain region 62b of the select transistor is coupled to the bit line B/L via the bit line contact.
Further, in such an EEPROM cell array, each of byte select lines (S/L1, S/L2, . . . ), which are in parallel with the bit line B/L and are of an identical conductivity type to the bit line B/L, is arranged every byte, and the common source line CSL is arranged every tens of bits and connected to the active source region like the flash memory cell array.
The EEPROM cell has a complicated structure as shown in FIGS. 4 and 5 to execute the erasing operation in the unit of byte, i.e., in the unit of 8 bits. The programming, erasing and reading operations of the EEPROM cell will be discussed in detail hereinbelow.
First, an erasing operation of the EEPROM cell refers to increasing the threshold voltage Vth of the cell from the initial level, about 0V, to about +5V by storing electrons into the floating gate. That is, by applying 20V to the selected word line and the byte select line and 0V to the bit line, electrons are introduced into the floating gate by the F-N tunneling via the tunnel oxide film.
A programming operation refers to dropping the threshold voltage Vth of the cell to less than -5V by removing electrons from the floating gate. That is, by applying a program voltage of about 13V to the selected bit line, 20V to the selected word line and 0V to the byte select line, the source and the bulk substrate, the electrons in the floating gate are removed to the bit line due to the potential difference between the selected bit line and the control gate.
For a reading operation, by applying a reading voltage to the selected bit line and the word line W/L and applying 0V to the byte select line, the source and the bulk substrate, a current path is formed by the bit line voltage in the case that the cell is programmed, while the current path is not formed in the case that the cell is erased and thus the threshold voltage is over 0V. Hence, the data is determined by using the presence or absence of the current path.
Comparing the flash memory device with the EEPROM device as described above, the flash memory device is useful for high integration due to small cell size but disadvantageous in that, since the minimum unit for erasing is a block, all cell data in a block should be reprogrammed even when rewriting fewer data bits. On the contrary, the EEPROM device has a disadvantage of lower integration due to a larger cell size, because an additional byte select line is needed and a unit cell is composed of two transistors. However, it also has an advantage that it takes short time to rewrite fewer bits of data because the erasing is performed in bytes.
To make use of the advantage of each device, a combined memory device has been recently proposed which uses flash memory cells of high integration and EEPROM cells of fewer bits (e.g., a few Kbits to hundreds of Kbits). In this device, the EEPROM cells are used when rewriting fewer data bits, while the flash memory cells are used when rewriting greater amounts of data. However, since the size of the EEPROM cell is greater compared to the flash memory cell and the structure of the EEPROM cell is different from that of the flash memory cell, when cells over tens of Kbits are used, the chip size is increased and the manufacturing process or the cell operation becomes complicated.